1. Field of the Invention
The invention relates to a semiconductor device and a method for forming a semiconductor device. More particularly, the invention relates to a capacitor for a semiconductor device and a method for forming the capacitor.
2. Brief Description of Related Technology
Each of a dynamic random access memory (DRAM), which is the most widely used semiconductor memory device, and a ferroelectric random access memory (FeRAM), which has attracted much attention recently, has a unit cell structure consisting of one transistor and one capacitor. The unit cell structure of the DRAM and FeRAM is a superior structure from an integration respect.
The capacitor of such semiconductor devices has a stacked structure including an upper electrode, a dielectric layer for charge storing, and a lower electrode. In a DRAM and a FeRAM, the capacitor is coupled to one active region of a transistor through a plug formed of doped polysilicon. The charge stored in the capacitor flow into a bit line through a channel of the transistor and another active region of the transistor.
Methods for forming a highly integrated DRAM or FeRAM, employing high dielectric material or ferroelectric material for forming a capacitor dielectric layer, respectively, are described below. As used herein, the term “dielectric material” can include a ferroelectric material and “dielectric layer” can include a ferroelectric layer.
An interlayer insulating layer and an etch barrier layer are formed on a semiconductor substrate on which a transistor and a bit line are formed. Thereafter, the interlayer insulating layer and the etch barrier layer are selectively etched to form a contact hole exposing an active region of the transistor, and a polysilicon plug is then formed in the contact hole to fill a portion of the contact hole.
Subsequently, a titanium layer is deposited on the substrate and a rapid thermal process is performed to form a titanium silicide (TiSix) layer by causing a reaction between silicon in the polysilicon plug and titanium in the titanium layer. The titanium layer remaining on the interlayer insulating layer is removed by a wet etching process. The TiSix layer is an ohmic contact layer reducing contact resistance between the polysilicon plug and a diffusion barrier layer to be formed over the polysilicon plug.
Next, a TiN layer is formed on the TiSix layer and the etch barrier layer. The TiN layer is then removed by a polishing process or an etching process until the surface of the etch barrier layer is exposed to leave the TiN layer only in the contact hole. The TiN layer plays the role of a diffusion barrier layer to prevent oxygen diffusing to the polysilicon plug or the substrate through a lower electrode of a capacitor during thermal treatment. Such a thermal treatment can be a part of a process for forming a high dielectric layer or a ferroelectric layer, for example.
Thereafter, a lower electrode layer, a high dielectric layer (or a ferroelectric layer), and an upper electrode layer are deposited in order and pattern to form a capacitor. It is difficult to use polysilicon as an electrode material. Instead of polysilicon, noble metals, such as platinum (“Pt”), iridium (“Ir”), and ruthenium (“Ru”); conductive oxides, such as RuO2 and IrO2; and conductive compounds such as TiN can be used to form the metal/insulator/metal(“MIM”) structure of a capacitor.
A high dielectric layer made of SrTiO3 (“STO”) or (Ba, Sr)TiO3 (“BST”), and a ferroelectric layer made of Pb(Zr, Ti)O3 (“PZT”), SrBi2Ta2O9 (“SBT”), (SrxBi2-y)(Ta1-zNbz)2O9 (“SBTN”), or (Bi, La)TiO3 (“BLT”) are generally formed at very high temperature (e.g., from about 600° C. to about 1000° C.) in an oxygen atmosphere.
When depositing a dielectric layer or performing a subsequent thermal treatment in an oxygen atmosphere, oxygen can diffuse into parts of the semiconductor device that are under the capacitor and cause problems such as formation of an isolation layer or a resistance material. For example, an isolation layer including SiO2 can be formed on the surface of the polysilicon plug by diffused oxygen. Moreover, in the case of forming a lower electrode on a polysilicon plug using metal, such as Pt, a resistance material, such as PtSi, is easily formed by the reaction of the metal and silicon at a temperature above about 250° C., for example. Therefore, the problem of increased resistance is possible.
To ameliorate the problem of resistance increase, a diffusion barrier layer is formed of TiN, as mentioned above. However, subsequent processing temperatures are limited to about 450° C. even if the barrier layer is formed of TiN, due to the potential for oxidizing TiN. Accordingly, a barrier material capable of effectively preventing the polysilicon being oxidized is desired. A triatomic barrier layer material, such as TiAlN, TiSiN, or TaSiN, is oxidized at a temperature as much as about 50° C. to about 100° C. higher than TiN. However, such a triatomic barrier layer is also easily oxidized at a temperature of over 550° C. That is, an insulating layer, such as a TiO2 layer, an Al2O3 layer, or a SiO2 layer, is formed on the surface of the triatomic barrier layer because oxygen diffused through the lower electrode reacts with the Ti-based nitride layer or the polysilicon plug during a process for forming a capacitor.
To secure the dielectric quality of a high dielectric layer, such as a layer made of STO or BST, and a ferroelectric layer, such as a layer made of PZT, SBT, SBTN, or BLT, the barrier layer preferably will resist or prevent oxidation of the polysilicon and resist or prevent oxidation of itself at a temperature over about 600° C.